The present invention relates to field effect transistors (FETs), and more specifically, to vertical-type FETs.
As demands to reduce the dimensions of transistor devices continue, new designs and fabrication techniques to achieve a reduced device footprint are developed. Vertical-type field effect transistors (vertical FETs) have recently been developed to achieve a reduced FET device footprint without comprising the necessary FET device performance. Vertical FETs are fabricated such that source/drain (S/D) regions are arranged at opposing ends of a vertical channel region.
The vertical orientation of the vertical FET allows for controlling the voltage rating as a function of the doping and thickness of the epitaxial layer, while the current rating is controlled as a function of the channel width. Accordingly, a vertical FET may sustain both high blocking voltage and high current within a compact semiconductor substrate (e.g., silicon substrate). Vertical FETs may also allow for relaxed gate lengths to better control device electrostatics, without sacrificing the gate contact pitch size.